1. Field of the Invention
The present invention relates to detection of data in a communications system, and, more particularly, to detection of servo repeatable run out (RRO) information from a channel.
2. Description of the Related Art
A read channel integrated circuit (IC) is a component of a modem hard disk drive, such as a hard disk drive found in many PCs. A read channel component converts and encodes data to enable the (e.g., magnetic) recording head(s) to write data to the disk and then read back the data accurately. The disks in a hard disk drive typically include many tracks containing encoded data, and each track comprises one or more of user, (or “read”) data sectors as well as “servo” data sectors embedded between the read sectors. The information of the servo sectors aids in positioning the magnetic recording head over a track on the disk so that the information stored in the read sectors may be retrieved accurately.
Repeatable run out (RRO) refers to a phenomenon that occurs due to an imperfect spindle upon which the disk rotates. An imperfect spindle might not allow the disk in the hard drive to spin properly at the disk's center. If the disk is not rotating at the center, then the track rotating under the head will not follow a circular trajectory, and hence the head might not be able to read the servo information properly. A similar phenomenon occurs when spindle imperfections were present at the tine the servo information was written to the disk. Even though the disk may spin properly in a different hard disk drive while reading the servo information, since the information was not written properly on a circular track, the head might not be able to read the servo information accurately. Thus, there is a need for a mechanism to properly guide the head to follow the trajectory of the track. A RRO data field in the servo information serves this purpose.
FIGS. 1A-1D illustrate one form of RRO (termed a one “f” run out) that results from an imperfect spindle. FIG. 1A shows radial position versus error when the error is zero, corresponding to the head tracking in a circular trajectory as shown by the dashed circle 102 on disk 103 of FIG. 1B. As shown in FIG. 1C, the error for one “f” run out varies as a function of the radial position, but the error at a given position repeats after one revolution of the disk. As shown in FIG. 1D, the one “f” run out results from the head tracking an oval path, shown by the dashed path 104 on disk 103. Since the error “repeats” itself from one revolution to another, techniques may be devised to compensate for the problem. By feeding positioning information about the “repeatable” error to servo control circuitry, the error may be corrected to position the head properly over the servo track. State of the art magnetic recording systems employ digital signal processing to detect servo data as opposed to older systems employing analog techniques.
FIG. 2 shows a conventional magnetic recording system of the prior art. Servo data is encoded by block encoders 201. Block encoders 201 may represent several different encoders associated with different fields of the servo data. The encoded servo information is written to the disk (or other recording medium) as servo sector information.
FIG. 3 shows the format of servo sector information 300. The servo sector information 300 comprises preamble 301 (e.g., a 2T pattern) that allows the system to recover the timing and gain of the written servo data. Preamble 301 may be followed by encoded servo address mark (SAM) 302, which is generally an identical identification address (fixed number of bits) for all servo sectors. SAM 302 may then be followed by encoded Gray data 303. Gray data 303 represents track number/cylinder information and may be employed as coarse positioning information for the magnetic head. Gray data 303 is followed by one or more burst demodulation fields 304. Burst demodulation fields 304 are employed as fine positioning information for the head over the track. Burst demodulation fields 304 are followed by RRO data field 305. Information in RRO data field 305 provides head positioning information to correct for RRO, which information is finer than that provided by the Gray data and coarser than that provided by the burst demodulation fields.
The format of RRO data field 305 is shown in FIG. 4. RRO data field 305 begins with DC erase 401, which is a predefined pattern that is generally either an all-zeros or an all-ones pattern. DC erase 401 is followed by RRO address mark (AM) 402, which is a bit pattern that is the same for all servo sectors. RRO AM 402 indicates when to start decoding RRO data and aids selection of the best sampling phase for decoding RRO data 403. RRO AM 402 is followed RRO data 403, which includes head-positioning information. RRO data 403 is followed by parity field 404, which includes parity bits employed for error detection/correction. Parity field 404 is followed by toggle bit 405, which brings the magnetization level back to whatever magnetization level the disk used in DC erase 401.
The servo preamble, SAM, Gray data, and burst demodulation fields are typically written by a servo track writer. However, the RRO data field following the last burst demodulation field is typically written by the read channel component. For detecting the servo preamble, SAM, Gray data, and demodulation fields, a digital phase-locked loop (DPLL) acquires the proper sampling phase based on the timing information provided by the preamble. However, for RRO detection, it is not desirable to write a preamble for format efficiency reasons. Hence, a detector does not know a priori the proper sampling phase (timing) to read the RRO information. Thus, reading RRO information is an “asynchronous” data detection process. Also, detection of the RRO address mark is prone to detection errors because the RRO detector may begin detection in the DC erase field without the proper sampling phase (i.e., there is no preamble to guide the timing loop). The number of detection errors increases when fewer bits are written as the RRO address mark for format efficiency reasons.
Returning to FIG. 2, the encoded servo information is read back by a magnetic recording head. Together, the process of writing to, storing on, and reading from the disk by the recording head may be modeled as magnetic recording channel 202. Data read from the disk is referred to as readback data. The readback data is equalized to a desired target partial response by equalizer 203 comprising continuous time filter (CTF) 220 followed by discrete time, finite impulse response (FIR) filter 221. Sampling of the signal from CTF 220 (shown in FIG. 2 by switch 222) is synchronous using the timing information from a DPLL (not shown in FIG. 2) when servo Gray and demodulation burst data are read, but is asynchronous when RRO data is read. The output of equalizer 203 is digitized and quantized by A/D converter 204, whose output is shown as ‘Y’ values.
The Y values are applied to Viterbi detector 205, which is a partial-response maximum-likelihood (PRML) detector. Constraints imposed by the servo encoder of block encoder 201 may be employed in the design of the Viterbi detector to decode the servo data optimally. The output of Viterbi detector 205 is applied to block decoder 207 to generate decoded SAM and Gray data. The output of Viterbi detector 205 (which Viterbi detector might employ a pruned trellis to enforce the coding constraints of the RRO encoder) is also applied to RRO detector 208. RRO detector 208 includes RRO address mark (AM) & best phase (BP) detector 209, which detects the RRO address mark and simultaneously detects the BP (corresponding to the middle phase bit of the RRO codeword). RRO data decoder 210 of RRO detector 208 employs the RRO AM and the BP to select samples for decoding into RRO data. The ‘Y’ values are also passed on to burst demodulator 206 to generate fine positioning information for the head over the track.
Other detectors employed for detection of servo information include peak detectors. In peak detectors, location and polarity of the peak (which are dependent on servo encoder constraints) serve to enable decoding of the data. The output of the peak detector may also be fed to an RRO detector for detecting the RRO information. Both peak and Viterbi detectors give very good performance when they use properly sampled signals for detecting the bits. The performance of these detectors degrades significantly when the samples are generated with timing errors.
An RRO encoder (such as included in block encoders 201) might transform each one-bit value of the RRO data into 3-bit values by repeating the one-bit value three times (i.e., “1” goes to “111” and “0” goes to “000”). If the constraint that no two transitions are adjacent is imposed on detection of encoded RRO data (termed a d=1 constraint and often employed for non-return-to-zero (NRZ) line coding), the trellis employed by Viterbi detector 205 is pruned to enforce this constraint (i.e., the constraint that neither “010” nor “101” bit patterns are allowed within the output bit stream of the Viterbi detector). Enforcing the d=1 constraint in a 16-state Viterbi detector defines the invalid states for d=1 constraint as 0010, 0100, 0101, 1101, 1011, 1010. The valid states for d=1 constraint are 0000, 0001, 0011, 0110, 0111, 1111, 1110, 1100, 1001, and 1000.
FIG. 5 shows pruning of the trellis of the Viterbi detector with the d=1 constraint. The left column represents the 16 possible states at time [k−1], and the right column represents the 16 possible states at time [k]. The bit-pattern in each state represents the four bits currently in the detector, with the least significant bit (LSB) representing the most recently received bit (i.e., the LSB of a state at time [n−1] is Y[n−1]). Thus, a single bit cycle is shown. In general, transitions from invalid states in the left column are pruned (have no transitions) to the right column, with the exception of states 2 (0010) and 13 (1101) whose transitions enable each state to be reached by at least one path. For these exceptions, the transitions are to invalid states that are pruned in the next cycle. Valid states having a pruned path are indicated by heavy solid lines, with the path from the valid to invalid state being pruned. Other valid states in the left column may permit transitions to invalid states in the right column to enable each state to be reached by at least one path. The transitions to invalid states are then pruned in the next cycle.
Since the sampling phase is not known when reading the RRO data field, a Viterbi detector is more prone to making errors. Due to the imposed d=1 constraint, only certain type of errors are possible. Since each bit is written thrice and because of the d=1 constraint in the Viterbi detector, the first and third bits are most likely to be affected, while the second (middle) bit is most likely to be preserved due to improper sampling phase. For example, an encoded user data stream of . . . 111 000 111 000 000 . . . input to the d=1 constraint pruned Viterbi detector is output as . . . 011 100 111 100 000 . . . (using the pruned 16-state trellis of FIG. 5). Identifying the middle bit detects the corresponding RRO data field. The RRO address mark is employed to identify which bits of the Viterbi detector output are the middle bits.
One technique of the prior art employed by RRO AM & BP detector 209 to identify middle bits, or the “middle phase” as the best phase, employs middle phase selection logic. For example, if 0101001 is the pattern used for RRO address mark, after encoding, this pattern becomes 000111000111000000111 (which is 21 bits). RRO sync and phase centering by detector 209 are accomplished by passing the data from the output of the pruned Viterbi detector through a sliding window. The data within the window is compared to the expected address mark for each phase of the bit (3T/bit, where Tis the bit period). The RRO address mark is found when the number of mismatches is less than a threshold (or equivalently, the number of matching bits is greater than or equal to the threshold). For example, if no tolerance is allowed for errors in the read RRO address mark, then all 7 bits of the RRO address mark must match, and the threshold for the number of matching bits is set as 7. Phase centering (selecting which is the middle bit) is accomplished by evaluating the number of matches on adjacent phases.
FIG. 6 illustrates one technique of phase centering of the prior art used by RRO AM & BP detector 209 to detect the “middle phase” as the best phase. Data C is a bit stream output from the Viterbi detector. If “0101001” is the pattern used for the RRO address mark, then, after encoding, this pattern becomes 000111000111000000111, shown as the Data C bit stream. The Data B and Data A bit streams are the Data C bit stream delayed, in time, by one and two bit periods, respectively. The bit streams are passed through a sliding window 601 and compared to the expected RRO address mark value. The sliding window effectively produces the following operations at every bit period T: A=B, B=C, and C gets the next bit from the Viterbi detector. The RRO address mark value is found when the number of mismatches is less than a threshold, or, equivalently, the number of matches is greater than or equal to the threshold. For the example of FIG. 6, a threshold of 7 for the number of matching bits would require that no mismatches exist. Phase centering (i.e., detecting the middle-encoded bit) is accomplished by counting the number of matches in the adjacent phases.
Other techniques employ digital interpolation with bit peak detection to detect the series of peaks of the RRO AM on a peak-by-peak basis. One or more digital interpolators are employed to interpolate the asynchronous samples from the receiver's A/D converter to generate one or more interpolated samples in between the asynchronous samples. Thus, each digital interpolator generates an interpolated sample corresponding to some phase relative to that of the sample timing of the A/D converter. One aspect of interpolation employs a phase-locked loop with phase error detection to generate synchronous interpolated samples. Such method is described in U.S. Pat. No. 5,835,295 to Behrens entitled “Zero Phase Restart Interpolated Timing Recovery in a Sampled Amplitude Read Channel,” filed Nov. 18, 1996, which is incorporated herein in its entirety by reference.